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After v1.0: Could consider splitting Svyrg in two
questionFurther information is requestedFurther information is requestedStatus: Open.#1161 In riscv/riscv-cheri;After 1.0 consider decomposing Zyhybrid
questionFurther information is requestedFurther information is requestedStatus: Open.#1160 In riscv/riscv-cheri;How to encode SEal/UNseal permission in RV32LYA
new extensionan optional proposal which adds to the base functionalityan optional proposal which adds to the base functionalityquestionFurther information is requestedFurther information is requestedStatus: Open.#1156 In riscv/riscv-cheri;- Status: Open.#1057 In riscv/riscv-cheri;
Should compressed instructions be a separate Zcy instead of implicitly part of Zca?
questionFurther information is requestedFurther information is requestedStatus: Open.#1048 In riscv/riscv-cheri;Consider Zacas with AMOCAS.Y instead of AMOCAS.Q for shared memory revocation
new extensionan optional proposal which adds to the base functionalityan optional proposal which adds to the base functionalityStatus: Open.#914 In riscv/riscv-cheri;Missing Zicond capability equivalents
new extensionan optional proposal which adds to the base functionalityan optional proposal which adds to the base functionalityStatus: Open.#834 In riscv/riscv-cheri;compartment switch speculation barrier
new extensionan optional proposal which adds to the base functionalityan optional proposal which adds to the base functionalityStatus: Open.#826 In riscv/riscv-cheri;pointer masking and executable memory
help wantedExtra attention is neededExtra attention is neededStatus: Open.#805 In riscv/riscv-cheri;Define RVYB profile and first ratification package
ratification blockerConsidered a blocker for ratificationConsidered a blocker for ratificationStatus: Open.#802 In riscv/riscv-cheri;- Status: Open.#770 In riscv/riscv-cheri;
Instruction for capability-aware system-level cache maintenance?
new extensionan optional proposal which adds to the base functionalityan optional proposal which adds to the base functionalityStatus: Open.#745 In riscv/riscv-cheri;